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Effective PCB Substrate Design Practices for IC Package Assembly: A Case Study

In the semiconductor package assembly process, achieving precision in substrate design is a crucial element. The substrate should be designed taking into account the ease of assembly. This applies to die attaching, both flip-chip and traditional die attach for wire bonding. In this article, we will look at a specific case study involving shortcomings of a substrate design, focusing on challenges that were faced during the assembly, die attach, and wire bonding stages.

Case Study Overview For COB Substrate Design

Recently, we faced significant challenges during a Chip-on-Board (COB) bonding job involving a two-die configuration. Au wire bonding the primary die was not a path but rather straightforward and encountered no issues. However, the secondary die presented a unique challenge due to the design of the PCB substrate.

Challenges Faced During Au Wire Bonding

Wire Bonding Parameter Optimization To Bond on ENIG-finished Au Vias for Bond Strength

The second die attach pad, or the die attach surface, was designed with Au vias instead of a continuous Au bonding pad covering the full surface like the primary die attach surface with Electroless Nickel Palladium Immersion Gold (ENEPIG) processed surface. Also, the Au vias were not ENEPIG finish but Electroless Nickel Immersion Gold (ENIG), requiring hours of parameter fine-tuning to achieve acceptable bond strength.

Spatial Constraints in Die Downbonding (GND) on Limited Au Via Surface

The primary challenge was the spatial limitation for downbonding from the die; the die itself covered more than 95% of the Au via surface that was supposed to be used for downbonding. Even with minimal epoxy overflow from all sides of the die, less than 150 micrometers, there was not enough exposed surface for downbonding.

Capillary Tool Risks with Restricted Space

Even with the extremely small capillary, high loop size and changing the PCB position and alignment there was no simply enough space to down bond with out the risk of the capillary tool hitting the side wall of the the die casing side wall chipping or even die crack.

 

Strategic Solutions and Best Practices For PCB substrate design

Ensure Die Attach Pad Is Sufficiently Spacious

Ensure that either the Au vias covered or Full Au surfaced die attaches surface is atleast 750um bigger than the die on all sides for down boding the pads at the edge of the die, and if the down bond is from a die pad from the middle or further away from edge of the die, make sure to leave at least 2 times the length of the bond pad to the edge of the die distance to form proper suitable wire loop size. 

Consider Alternative Grounding Options

Strategically place spare bond pads/vias around the die attach surface to cater to errors caused by the die attach/wire bonding mishaps. It is always better to design the substrate for versatility rather than for small substate size for small volume builds for R&D purposes where the main purpose of the build is for proof of concept or specific function testing.

Implement Design for Manufacturability (DFM)

Before sending the pcbdoc/cad files to the PCB manufacturer for substrate fabrication, always involve the assembly engineer or assembly house in general to make sure that die attach and wire bonding can be done as intended. Their experience can inform the design adjustments that accommodate real-world assembly challenges.

 

PCB with a die attached pad barely larger than the die, showing inadequate space for ground connections and high risk of die damage
Challenges in PCB Die Attach: Limited Space and Bonding Risks during bonding.
PCB with gold grounding wire expertly bonded to vias away from the cramped die attach pad to avoid die damage.

Conclusion

The case study presented demonstrates the importance of thoughtful substrate design in semiconductor package assembly. By adopting these best practices, assembly facilities can improve their capability to handle complex packaging scenarios, thereby enhancing overall reliability and efficiency in semiconductor manufacturing. These strategies help in addressing immediate problems and also serve as proactive measures to prevent future issues, ensuring smoother operations and higher quality outcomes in the assembly process.

Please don’t hesitate to contact us for you PCB Substrate Design, PCB Substrate Fabrication and Package Assembly need. 

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Wire Bonding Techniques in Semiconductor Packaging

Wire bonding is a crucial process in semiconductor packaging. The process uses tiny wires, um in diameter wires to connect the semiconductor chip to the substrate. Even though newer technologies WLCSP devices with direct flip chip capabilities, wire bonded devices are used for the majority of applications. 

Three main types of wire bonding processes are typically used.

Thermosonic bonding: 

Technique heat, force, and ultrasonic energy are applied to the wire to make a bond connection between the wire and the chip or substrate. Few decades back thermosonic bonding was limited to Au (Gold) wires but due to increasing Au prices, for industrial high volume application, Cu wires are now being used. 

Thermosonic bonding

Ultrasonic Bonding: 

Mainly used for Al (aluminum) wire boning, ultrasonic bonding uses only ultrasonic energy for bonding purposes. Since no heat is used, Ultrasonic bonding is usually done without the use of a heating element (for Au and Cu wire bonding the substrate is heated 150C and above). Process relays on pressure and vibration to achieve a cold weld between the surfaces. 

Ultrasonic Bonding

Thermocompression Bonding: 

This technique relies on heat and force but does not use ultrasonic energy. Using a bonding tool heat and force is applied to the wire making it deform and connect with the bonding surface. Often used with Au wire bonding due to its malleability, Thermocompression bonding with Au wires are used when ultrasonic energy might damage the device. 

Thermocompression Bonding

Each method of wire bonding offers its own unique advantages and chooses based on the specific needs of the semiconductor device application. This may be the choice of wire material, desired strength, or reliability.  Intech Technologies is here to discuss your specific requirement and offer our expertise on the desired application. Please feel free to contact us and discuss any of your packaging needs.